COMMENT ⊗   VALID 00011 PAGES
C REC  PAGE   DESCRIPTION
C00001 00001
C00003 00002		This section  describes  the differences  between the  PDP-10
C00009 00003	ADDRESS SWITCHES AND CONDITIONS
C00012 00004	STORE CYCLE DIFFERENCES
C00015 00005	PRIORITY INTERRUPTS
C00019 00006	UUO's AND UNIMPLEMENTED INSTRUCTIONS
C00023 00007	MISCELLANEOUS DIFFERENCES
C00026 00008		STATUS REGISTERS
C00028 00009	3.	CONO APR,
C00030 00010	SUMMARY OF I/O DEVICES					 
C00032 00011	PDP-6 I/O BUS
C00034 ENDMK
C⊗;
	This section  describes  the differences  between the  PDP-10
and  the PDP-6.  It  also describes the modifications  that have been
made.

	The  PDP-10   and  the   PDP-6  are   not  entirely   program
compatible.  However,    the differences  between  the  two machines,
except  the  floating  point  instructions,  are  very  minor.    The
following list is  as complete as possible.   This section supercedes
SAILON No.47 and No.47 Supplement 1.


FLOATING POINT INSTRUCTIONS

	The  instruction  additions  and  changes  on the PDP-10 were
designed with the specific intention of facilitating double precision
floating point calculation and cleaning up the operation of the PDP-6
arithmetic instructions.

1.	The  PDP-6  does  not  have  the  UFA  (130)  and  DFN  (131)
instructions.

2.	The low order word of the FxxL instructions is  different  on
the two machines.

3.	The PDP-10 FxxRI instructions are FxxRL on the PDP-6.

4.	The  PDP-6 does not have the divide check, floating overflow,
and floating exponent underflow flags.  On the  PDP-6,  the  floating
overflow flag is replaced with the PC change flag.

5.	Rounding  of  FxxR instructions is handled in a different way
on the  PDP-6.   When  the  PDP-6  rounds  a  negative  number  whose
low-order part is exactly one-half, the round occurs toward zero.  On
the PDP-10, one-half is rounded to give the more negative result.

6.	Any floating add, subtract, or multiply instruction in  which
the  only  significant  bits  of the answer are in the low-order word
before normalizing, produces a  normalized  non-zero  result  on  the
PDP-10.  On the PDP-6, the bits are lost.



PROCESSOR FLAGS

1.	The PDP-6 PC change flag replaces the floating overflow  flag
in the PDP-6 status word, PC word, and the JFCL instruction.

2.	The PDP-6 does not have a divide check  flag  or  a  floating
exponent underflow flag.

3.	The  CPU  and  PI  status  bits are slightly different.  (see
Status Register section)

ADDRESS SWITCHES AND CONDITIONS

1.	The  address  switches  on  the  PDP-6  are compared with the
unrelocated address rather than the relocated address.

2.	The  PDP-6  has  been  modified  to  have  address  condition
switches  like those on  the PDP-10.   These switches  are located in
166 bay 1.

3.	The PDP-6 lacks the Address Break feature.



PDP-6 EXTRA MEMORY REFERENCES

The PDP-6 makes some unnecessary memory references  that  the  PDP-10
does not make.  For example:

	SETZ AC,-1

PDP-6.	Location  777777 is fetched from memory which may result in
a protection violation or a non-ex mem.

PDP-10.	Location 777777 is not fetched.

	The SKIPx  instructions on  the PDP-6  always store the  data
redundantly.   NEVER use  a SKIP instruction  on the PDP-6  to test a
flag set by the PDP-10.



BYTE INCREMENT  (IBP, ILDB and IDPB)

1.	PDP-6
If  a  carry  from  the  address  field into the index register field
occurs while incrementing the byte pointer, the new index register is
used for the effective address calculation of the byte pointer.

2.	PDP-10
If the same carry occurs  on the PDP-10, the old index  field is used
for  the  effective address  calculation unless  an  interrupt occurs
after the byte pointer  is incremented and before  the LDB or DPB  is
started.  In  this case, the new  index field is used  and the result
is  identical to that on  the PDP-6.  Since the  results in this case
are likely to be unpredictable,  one might be cautious in  using this
feature.

3.	The PDP-10 has been modified so that  an IBP instruction with
a  non-zero AC  field will  load the AC  with the  (incremented) byte
pointer.
STORE CYCLE DIFFERENCES

The PDP-6 stores the results of any instruction in the order: memory,
AC1,  AC2.   The PDP-10 stores the results in the order: AC1, memory,
AC2.  Two instructions behave slightly differently as a result.

     POP AC, AC

   a.    PDP-6:		(AC)-1000001→AC
   b.    PDP-10:	((AC)r)→AC

	BLT when:
   a.   Loading the AC's over the BLT pointer,and
   b.   An interrupt occurs,and
   c.   The memory word being transfered is being written over
	the pointer AC,and
   d.   The BLT still has more transfers to go.

	On the PDP-6 the  pointer  word  is  written  over  the
   memory word.    The instruction can reasonably continue with
   the updated pointer.  On the PDP-10 the updated  pointer  is
   destroyed  by  the  memory  word.     When  the  instruction
   continues, the result is a BLT using the memory  word  as  a
   pointer.     The  difference is only in the magnitude of the
   loss. Reasonable programming won't be bothered with this.





DIFFERENCES IN THE SUBTRACT ALGORITHM

PDP-6:
	Ones complement the AC,  2's  complement add, ones complement
the result (3 steps).

PDP-10:
	Direct 2's complement subtract (1 step).

	The difference results in the CRY0 and CRY1 flags on the
    PDP-6 being the complement  of  the  results  for  the  same
    subtraction  on  the  PDP-10. For example, say SUBI 1,105 on
    the PDP-6 resulted in the CRY0 and CRY1 flags being 1 and  0
    respectively;  The  PDP-10  would  set the flags to 0 and 1.
    (This assumes that both were 0 initially.)
PRIORITY INTERRUPTS

The PDP-6 may only have a JSR in the interrupt locations in order  to
call  an interrupt routine and enter executive mode.   The PDP-10 may
have a JSR, PUSHJ, or JSP.  Only these instructions store PC flags so
if some  other instruction were  used the  processor would not  enter
EXEC  mode, and making a  correct return from the  interrupt would be
impossible.

The PDP-6 allows interrupts to occur at two places in an instruction:
Prior   to  the  instruction  fetch  and  in  the  effective  address
calculation loop.  The PDP-10 allows interrupts only in the effective
address calculation loop.

	This difference shows up  when  the  PC  exceeds  memory
    bound   for  a  user-mode  program  and  an  illegal  memory
    reference occurs.   If the interrupt program recognizes  the
    illegal  memory  reference,  turns  off  the  illegal memory
    reference flag, and tries to get  out  of  the  APR  channel
    quickly  by  requesting  an  interrupt  on  a lower priority
    channel and dismissing the APR  interrupt  to  the  PC  word
    (unmodified from the time of the interrupt), the result is:

PDP-6:	Everything works fine because the interrupt on  the
	lower  priority  channel is recognized prior to the
	instruction fetch.

PDP-10:	Another illegal memory reference interrupt  results
	because   the   instruction   fetch    (using   the
	out-of-bounds PC)  occurs before the  interrupt  on
	the lower priority channel is recognized.

When the PDP-6 makes an illegal memory  reference  from  a  user-mode
program it restarts at the beginning of the instruction timing chain.
The PDP-10 restarts in the instruction chain after the place where  a
instruction is normally fetched, resulting in a 0 instruction.  Also,
the interrupt system has not  set  up  to  trap  the  illegal  memory
reference   during  the  effective  address  calculation  for  the  0
instruction.  The result of all this is:

PDP-6:	The  illegal  memory  reference  flag  interrupt  occurs
    before the beginning of the next instruction.

PDP-10:	Executive  location  40  has  a 0 written into it (the 0
    instruction results in a UUO which is dumped into  executive
    location  40).   The  interrupt  occurs during the effective
    address  calculation  for  the  instruction   in   executive
    location 41.
UUO's AND UNIMPLEMENTED INSTRUCTIONS

    PDP-6
	a.	UUO's  040-077  trap to executive locations 40
	and 41.

	b.	UUO`s  000-037 trap to user locations 40 and 41 if in
	user mode.  If in exec mode, they trap to executive locations
	40 and 41.  (Note that 000 is considered a legal user UUO.)

	c.	Unimplemented instructions  100-117,  131,  and  243,
	when executed, have no effect (no-op).

    PDP-10
	(The PDP-10 is usually operated in MA TRAP OFFSET mode.  This
	moves the EXEC trap locations from 40-61 to 140-161.)

	a.	UUO`s 000 and 040-77 trap to executive  locations 140
	and 141.

	b.	UUO`s  001-037 trap to user locations 40 and 41 if in
	user mode.  If in exec mode, they trap to executive locations
	140 and 141.

	c.	Any  unimplemented  instruction from 100-177 traps to
	executive locations 160 and 161.

	d.	Unimplemented   instruction   257   results   in   no
	operation.

NEW INSTRUCTIONS

	XCT 1,E

	XCT 1,E in EXEC mode causes the  instruction in location E to
be  executed with  the memory reference(s)  relocated by  the current
contents  of  the  protection/relocation  register.    The  effective
address calculation  is done without  relocation.   In the case  of a
byte  instruction,   the byte  pointer is  fetched from  exec address
space.     The   relocation  applies   only   to  the   actual   data
fetch/store(s). If  the effective address of the  instruction in E is
in the  range 0-17  it is  relocated (i.e.,  NOT mapped  to  physical
AC's).

	FIX AC,233000

	The FIX instruction has been added  to  the  PDP-10  and  the
PDP-6. FIX on the 10 is op-code 247.  The FIX instruction on the 6 is
op-codes 120 through 130 inclusive and 247.

	There is  a CONS  instruction on  the PDP-6.   If you  really
want to know about the CONS instruction, look at the 166 prints. 
MISCELLANEOUS DIFFERENCES

	JFFO (op-code 243) is a no-op on the PDP-6.

	The PDP-10  has second  protect and  relocate registers;  the
PDP-6 does not.

	It  is   sometimes  desirable   to  pick  between   seemingly
equivalent instructions on  the PDP-6 to get the maximum speed.  This
is less often necessary on the PDP-10.

	When the READ IN switch is actuated  on the PDP-6, the effect
is  the same  as pushing  start, except that  the machine  will start
executing in shadow memory (real core locations 0-17, not  the AC`s).
The  PDP-10 however  sends a  pulse  on the  I-O buss  to a  specific
device to load core.

	The PDP-6 turns off the byte  increment suppression flag when
the  PC and flags are  being saved at a  UUO or PI trap.   The PDP-10
turns it off whenever the PC and flags are saved.

	The MI cannot be loaded by a program on the PDP-6.

	JRST 2,A(XR) may be used to get  an indexed return along with
flag  restore from  the index  register.   However  on the  PDP-6 the
flags are restored  from the left  half of the  full-word sum of  the
contents of XR and the JRST  instruction itself.  This is not usually
the desired  effect,  and indirect addressing should be used instead.
On the PDP-10 this instruction restores the flags from  the left side
of XR which is considered the correct operation.

	The  PDP-10  has  been  equipped   with  a  System  Clobbered
Detector. This device  will interrupt the APR if it is enabled and it
detects a write reference to absolute locations 40000 to 137777.

The detector is enabled by
	  DATAO PTR,[1]		;Bit 35 is the enable.

It is disabled by
	 DATAO PTR,[0]

The System Clobbered  flag is bit  18 of CONI  APR, and that  flag is
cleared by a CONO APR, with bit 20 set.
	STATUS REGISTERS

1.	PC word

BIT	ABBREVIATION	PDP-10 FUNCTION		PDP-6 FUNCTION
						(if different)
0	AROV		AR overflow flag
1	CRY0		AR carry 0 flag
2	CRY1		Ar carry 1 flag
3	FOV		AR floating overflow	PC change flag
			flag
4	BIS		Byte increment
			suppression flag
5			User-mode flag
6			IOT User-mode flag
11	FXU		Floating point exponent	Not used
			underflow flag
12	DCK		Divide check flag	Not used



2.	CONI APR,

BIT	PDP-10 FUNCTION		PDP-6 FUNCTION
    _				(if different)
18 |	System Clobbered	Not used
19 |	PDL overflow flag
20 |_	IOT user mode flag
21 |	Address break flag	Not used
22 |	MEM protect flag
23 |_	Non-ex-mem flag
24 |	Not used
25 |	Clock interrupt enable
26 |_	Clock flag
27 |	Not used
28 |	AR FOV interrupt enable	PC change interrupt enable
29 |_	AR FOV flag		PC change flag
30 |	MA TRAP OFFSET		Not used
31 |	AR OV interrupt enable
32 |_	AR OV flag
33 |	\
34 |	 > Processor PI channel
35 |_	/
3.	CONO APR,

BIT	PDP-10 FUNCTION			PDP-6 FUNCTION
    _					(if different)
18 |	Clear PDL overflow flag
19 |	I/O bus reset
20 |_	Clear System Clobbered Flag	Not used
21 |	Clear ADDR break flag		Not used
22 |	Clear mem protect flag
23 |_	Clear non-ex-mem flag
24 |	Clear clock interrupt enable
25 |	Set clock interrupt enable
26 |_	Clear clock flag
27 |	Clear FOV interrupt enable	Clear PC change interrupt enable
28 |	Set FOV interrupt enable	Set PC change interrupt enable
29 |_	Clear FOV flag			Clear PC change flag
30 |	Clear AROV interrupt enable	
31 |	Set AROV interrupt enable
32 |_	Clear AROV flag
33 |	\
34 |	 > Processor PI channel
35 |_	/



4.	CONI PI,

BIT	PDP-10 FUNCTION			PDP-6 FUNCTION
    _					(if different)
18 |	Power failure flag		Not used
19 |	Parity error flag
20 |_	Parity error interrupt enable	Not used
21 |	1 \
22 |	2  |
23 |_	3  |
24 |	4   > PI channels in progress	Not used
25 |	5  |
26 |_	6  |
27 |	7 /
28 |	PI system on
29 |_	1 \
30 |	2  |
31 |	3  |
32 |_	4   > PI channels enabled
33 |	5  |
34 |	6  |
35 |_	7 /
SUMMARY OF I/O DEVICES					 

	This  section  lists  the I-O devices on the computers at the
project.   It supercedes SAILON No.   24,  PDP/6  I/O  DEVICE  NUMBER
SUMMARY by Steve Russell and SAILON No. 25, THE MISCELLANEOUS OUTPUTS
by Steve Russell.

PDP-10 I/O BUS

Device Number	Device

000		PDP-10 APR					APR
004		PDP-10 PI system				PI
010		167 High speed data channel			IOP
100		PDP-10 paper tape punch				PTP
104		PDP-10 paper tape reader			PTR
120		PDP-10 console teletype				TTY
124		Line printer					LPT
200		136 data control for dectapes and magtapes	DC
210		551 dectape control				UTC
214		Dectape status					UTS
220		516 magnetic tape control			MTC
224		Magnetic tape status1				MTS
230		Magnetic tape status2				MTM
300		630 teletype scanner				DCSA
304		Teletype scanner				DCSB
310		Microswitch Keyboard Scanner			DKB
340		Video Switch					VDS
344	IOB EXT
350	   .
354	   .
360	   .
364	   .
370	   .
374	IOB EXT
404		Television interface and spacewar buttons	TV
430		III Display system control			DP
434		III Display system keyboard scanner		KBD
444		Librascope disk interface			DSK
500		IBM Selector Channel				PMP
504		IBM Selector Channel				IBM
510		Data Disc controller				DDD
774		Audio Switch					...

PDP-6 I/O BUS

Device number	Device

000		PDP-6 APR					APR
004		PDP-6 PI system					PI
100		PDP-6 paper tape punch and Calcomp plotter	PTP
104		PDP-6 paper tape reader				PTR
120		PDP-6 console teletype				TTY
204		136 data control in Kluge bay			DCB
340	IOB EXT
344	   .
350	   .
354	   .
360	   .
364	   .
370	   .
374	IOB EXT
410		Sierra Camera driver
420		Electric arms
424		Analog to digital converter			AD
440		Xerox Graphics printer				XGP
500		Hand-Eye kludge D-to-A's and stepping motor drives
600		Misc. outputs (all channels)
700		Misc. outputs (channels 40 through 77)
730		Electronic clock				PCLK